Semiconductor integrated circuit devices typically comprise multiple layers of vertically stacked metal interconnect layers with dielectric materials disposed between them. As microelectronic circuits become increasingly integrated, the surface area for the circuits is being reduced with an increase in the number of vertically stacked metal interconnect layers. It is anticipated, for example, that chips having an area of one square centimeter could potentially have tens to hundreds of dense interconnect layers to effectively use all elements on the die. Thus, there is an increased need for improved methods of coupling interconnect layers.
Electrical connections between interconnect layers are achieved with contact holes and via holes placed in the dielectric layers as they are fabricated. A contact hole is a conduit for electrically connecting the metal layers to the semiconductor substrate, and a via hole is a conduit for electrically connecting two metal interconnect layers, which may be adjacent or distal layers. Typically, the contact and via holes are formed with etching techniques that require use of high temperatures and reactive solvents to strip the photoresist and remove other residues and mobile ion contaminants. There are drawbacks, however, with these processes.
For example, FIGS. 1A through 1G are diagrammatic cross-sectional views depicting exemplary processing steps involved in constructing an integrated circuit device with post contact and via holes. In FIG. 1A, there is shown a semiconductor substrate 10, having disposed thereon a plurality of transistors or diodes, shown generally as active regions 12. A first dielectric layer 14 is deposited over the substrate, which may be comprised of a thin film of silicon-dioxide, SiO.sub.2, or other dielectric materials such as a-Ta.sub.2 O.sub.5, a-TiO.sub.x, or x-(Ba,Sr)TiO.sub.3. An etch stop layer 16 comprised, for example, of silicon nitride, may be deposited over the dielectric layer. Contact holes 18 (shown in FIGS. 1C-1D) are formed in the device of FIG. 1A to provide contact with the active regions 12 of the substrate 10.
The etching of the device to form the contact holes 18 often is performed with a photoresist mask and dry etching process involving use of a plasma RIE process and a reactive gas, such as CHF.sub.3 or SF.sub.6. Referring to FIG. 1B, a photosensitive mask may be used to deposit a photoresist layer 20, over selected regions of the etch stop layer 16. The exposed portions of the etch stop layer 16 and dielectric layer 14 are controllably etched with the reactive etchant to expose the active regions 12 and provide contact holes 18 (FIG. 1C). However, referring to FIG. 1C, the photoresist layer 20 needs to be removed, that is, to provide the structure of FIG. 1D. The stripping of this layer 20 is generally performed at high temperature using an O.sub.2 -containing plasma, e.g., at about 250.degree. C.
The high temperatures used to strip the photoresist introduces complications to the process, as the high temperatures may cause oxidation of the materials at the bottom of the contact or via holes (i.e. these materials may comprise silicon, titanium nitride, or aluminum). The photoresist process may cause mobile ion contaminants (i.e., Na+, Cl-, fluoride species, or other ionic organic compounds), to become embedded in the wafer surface (which usually is comprised of silicon dioxide [SiO.sub.2 ]). These contaminants should be removed as they may cause electrical device or crystal defects, lower oxide breakdown fields, and overall degrade the performance and yield of the device. To remove the contaminants, often an isotropic oxide etch is performed (e.g., using a dry plasma process and gas mixtures of CF.sub.4 /O.sub.2 or NF.sub.3 /He). Other methods may be used, such as cleaning with an HF acid solution. In any case, the high temperatures associated with the photoresist strip process introduce oxidation or mobile ion contamination problems which adversely impact upon product yield and reliability and require the use of additional processing steps.
Additionally, after the photoresist 20 is stripped, photoresist residues may remain, (e.g., on the surface of the etch stop layer 16), and the surface and sidewalls of the substrate at the contact or via holes 18 may contain etchant residues. These residues are often comprised of titanium and aluminum-containing films (non-volatile etch products) which frequently will adhere to the sidewalls of the contact or via holes. Thus, once the photoresist is stripped, the structure needs to be cleansed. This is typically done with a solution such as H.sub.2 SO.sub.4 /H.sub.2 O.sub.2 or solutions commonly known in the trade as EKC-265 (a solution comprising hydroxyl amine, 2-(2-aminoethoxy)ethanol, cathechol, and an alkaline buffer), and ACT-CMI (a solution of dimethylacetamide and diethanol amine). A further oxide etch or cleansing step may then be performed to remove the mobile ion contamination and oxidized layers.
This photoresist and etching process may be continued to provide further via holes as the fabrication of the integrated circuit device is continued, and as each group of via holes are formed, the cleaning process is repeated. For example, FIG. 1E shows the contact holes 18 of FIG. 1D filled with a metal interconnect structure 26, providing an electrical connection to the active regions 12. On the interconnect structures 26 there is disposed a protective layer 28 and a dielectric layer 30. A photoresist layer 31 is shown deposited over selected regions of the dielectric layer 30, and the plasma etching process is performed to provide via holes 32 at the exposed regions, as shown in FIG. 1F. The photoresist layer 31 of FIG. 1F may then be removed to provide the structure of FIG. 1G. As previously discussed, the photoresist 31 is stripped at high temperatures, creating mobile ion contamination. A cleansing solution is applied to remove etchant or photoresist residue from the etched surface 30, and from the sidewall or top surface of the vias 32. A further oxide etch or cleansing step is then applied to address the mobile ion contamination. These processes may be continued as additional layers are applied, resulting in multiple interconnect regions provided through many via holes etched during fabrication, followed by many cleaning steps.
Although the etching process described above is advantageous for producing a multi-layered integrated circuit device with a plurality of interconnects, there are drawbacks associated with the photoresist strip and residue removal process. The use of high temperatures in the photoresist strip process is disadvantageous as it creates the potential for mobile ions being embedded in the substrate, requiring additional etching or cleaning steps. The solvents used in removing the residues create potential for solvent build-up and corrosion of the circuit device. As circuit devices are integrated and the surface area of the devices is reduced, the diameter of the vias is likewise reduced, which increases the likelihood that solvents will become trapped in the vias and increases the potential for corrosion. Each cleansing step increases the process time, and especially when a multi-tiered structure is being fabricated, each additional step can significantly increase the overall processing time. The use of reactive solvents also creates disposal issues and health concerns.
Accordingly, there is a need for improved methods of stripping photoresist layers and removing residues and contaminants involved in fabricating post vias in integrated circuits. This invention addresses these needs. Further advantages may appear more fully upon consideration description below.